International Workshop on Stress Management for 3D ICs Using Through Silicon Vias (2011 March 17 : Santa Clara, Calif.),
Stress-induced phenomena and reliability in 3D microelectronics : Kyoto, Japan, 28-30 May 2012 / editors, Paul S. Ho, University of Texas, Texas, USA, Chao-Kun Hu, IBM T.J. Watson Research Center, New York, USA, Mark Nakamoto, Qualcomm Incorporated, California, USA, Shinichi Ogawa, Advanced Industrial Science and Technology, Ibaraki, Japan, Valeriy Sukharev, Mentor Graphics Corporation, California, USA, Larry Smith, SEMATECH, New York, USA, Ehrenfried Zschech, Frauhofer Institute for Ceramic Technologies and Systems, Dresden, Germany.
Three-dimensional integrated circuits -- Congresses.
Interconnects (Integrated circuit technology) -- Defects -- Congresses.
Metal-metal bonds -- Congresses.
Strength of materials -- Congresses.
Nanostructured materials -- Congresses.
Semiconductors -- Congresses.
Copper -- Electric properties -- Congresses.
Electronic books. local
Ho, P. S., editor.
Hu, Chao-Kun. IBM T.J. Watson Research Center, New York, USA, editor.
Nakamoto, Mark, editor.
Ogawa, Shinichi, Dr., editor.
Sukharev, Valeriy, editor.
Smith, Larry. SEMATECH, New York, USA, editor.
Zschech, Ehrenfried, editor.
International Workshop on Stress Management for 3D ICs Using Through Silicon Vias (2011 July 13 : San Francisco, Calif.),
International Workshop on Stress Management for 3D ICs Using Through Silicon Vias (2011 October 12 : Dresden, Germany),
International Workshop on Stress-Induced Phenomena in Microelectronics (12th : 2012 : Kyoto, Japan),